EJEEE
https://doi.org/10.62909/ejeee.2024.007 Edison Journal for Electrical and Electronics Engineering
Article
End-to-End Quantization Co-Design for MHz GaN Converters
using Dither and Sigma-Delta Modulation
Nuha Adnan Al-Obaidi 1, , and Ali K. Nawar 1,
1 Department of Electrical Engineering, Collage of Engineering, Wasit University, nuhaa302@uowasit.edu.iq
* Correspondence: ali.khalaf@uowasit.edu.iq;
Abstract: We study end-to-end quantization in digitally controlled MHz-range GaN DC–DC con-
verters, spanning the analog-to-digital converter (ADC), fixed-point controller, and digital pulse-
width modulator (DPWM). A simulation framework sweeps ADC and DPWM resolutions across
buck, boost, and inverting buck–boost converters at 1, 5, and 10 MHz, reporting regulation bias,
output ripple, and limit-cycle occurrence. A simple metric compares the DPWM step (mapped to
) to the ADC least-significant bit and accurately predicts the onset of limit cycles: designs with
avoid limit cycles in all surveyed cases. The results yield practical rules: boost and buck–boost
require finer DPWM than buck due to larger ; dithering and first-order sigma–delta ()
modulation provide roughly one to two effective DPWM bits at 1 MHz; and increasing switching
frequency tightens timing margins but can be offset by modest DPWM resolution or reduced digital
delay. Validation includes analytic–simulated slope agreement, –versus–limit-cycle slices, and ro-
bustness to parasitic spreads, ADC noise, and jitter. These findings provide concise, quantitative
guidance for selecting ADC and DPWM resolutions to meet – ripple targets without
limit cycles in MHz GaN converters.
Keywords: GaN, DC–DC converters, digital control, quantization, Limit Cycles, DPWM
1. Introduction
GaN switches make MHz switching practical and unlock impressive power density
and transient speed in DC–DC converters. The price, however, is a far tighter digital con-
trol problem. In a fully digital loop, the analog-to-digital converter (ADC) samples the
output into discrete codes, a fixed-point controller updates the duty command, and a dig-
ital pulse-width modulator (DPWM) turns that command into on/off pulses. Each block
introduces quantization that behaves like a nonlinear disturbance. Classic analyses show
that these quantizers can drive limit-cycle oscillations (LCOs) with poorly predictable fre-
quency and amplitude [1], complicating electromagnetic interference (EMI) behaviour. At
the same time, tight regulation targets on the order of a few millivolts demand high ADC
and DPWM resolution [2], which costs power and area.
This work focuses on end-to-end co-design of resolution across the ADC, controller
arithmetic, and DPWM for converters operating in the MHz range. We revisit how coarse
quantization affects steady-state accuracy, dynamic response, stability margins, and EMI,
and we ground the discussion with simulation evidence and simple design rules that gen-
eralize across topologies. Our discussion builds on prior studies of quantization-induced
LCOs and resolution trade-offs [3] and [4], but emphasizes practical guidance for modern
GaN converters.
1.2 Literature Survey
Digital control of switch-mode converters has a deep literature showing how finite
DPWM and ADC resolution
Citation: Al-Obaidi, N. A. and Na-
war A. K., End-to-End Quantization
Co-Design for MHz GaN Converters
using Dither and Sigma-Delta Modu-
lation. 2025. 3. p. 65-74
Academic Editor: Asst. Prof. Dr.
Amir Seyyedabbasi
Received: 24/10/2025
Revised: 1/12/2025
Accepted: 9/12/2025
Published: 14/12/2025
Copyright: © 2025 by the authors.
Submitted for possible open access
publication under the terms and
conditions of the Creative Commons
Attribution (CC BY) license
(https://creativecommons.org/license
s/by/4.0/).
EJEEE 2025, Vol.3 66 of 75
Table 1. Representative studies on quantization in digitally controlled DC–DC converters.
Alters loop gain and can even induce limit cycles; these fundamentals and their de-
sign implications are well established in classic and modern references [1, 6-8]. Practical
guidance on budgeting resolution, latency, and sampling—together with implementation
tips for real power stages—appears in seminar and monograph treatments [9, 10], [11].
Recent studies quantify how ADC quantization propagates through cascaded cur-
rent/voltage loops and affects accuracy and stability, while also surveying remedies for
low-resolution limit cycling [12], [13]. On the implementation side, a wide range of
DPWM architectures—from ASIC to FPGA with sub-clock interpolation—has been devel-
oped to push effective time resolution; these works review alternatives, identify trade-
offs, and demonstrate concrete techniques for fine duty-cycle granularity [14], [15].
Timing jitter and switching uncertainty shift effective duty cycle, impact efficiency,
and tighten timing budgets, motivating both analysis and mitigation in digital controllers
[16]. To curb EMI while preserving regulation bandwidth, spread-spectrum and related
frequency-modulation strategies have proven effective, with recent results clarifying co-
existence and limits in practical systems [17], [18], [19]. Pushing into the multi-MHz re-
gime—often with GaN devices—exposes new trade-offs among parasitics, sampling de-
lays, and quantization; demonstrations span very-high-frequency prototypes and PWM-
controlled MHz converters [20], [21]. Modern digitally controlled converters also illustrate
mode-management features such as automatic PFM–PWM transition to protect light-load
efficiency without sacrificing precision at higher loads, and scaling to interleaved, trac-
tion-class GaN systems highlights the approach’s practicality at power and phase count
[22], [23].
Table (1) reviews representative studies on quantization in digitally controlled DC–
DC converters. Early demonstrations by Prodić et al. showed 1 MHz digital buck opera-
tion with practical guidance on allocating ADC and PWM bits [5]. Patella et al. introduced
repeating duty patterns (dither) to achieve near 12-bit effective resolution from a 6-bit base
at 1 MHz [2]. Peterchev and Sanders analysed how ADC and DPWM quantizers drive
Reference
Topology
ADC (bits)
DPWM (bits)
Key findings
Prodić et al.,
2001 [5]
Buck
1 MHz
8–10
8–10
Early digital buck implementa-
tion and practical guidance on
ADC/PWM resolution to meet
output accuracy.
Patella et al.,
2003 [2]
Buck
1 MHz
6
6 (+ dither)
Demonstrated repeating duty
patterns (dither) to realize 12-
bit effective resolution at 1 MHz.
Peterchev &
Sanders, 2003 [1]
Buck (model)
–
Variable
Variable
Analyzed steady-state LCOs
from ADC/DPWM quantizers;
derived no-LCO conditions and
introduced controlled DPWM
dithering.
Peng et al., 2007
[3]
Buck (model)
–
Variable
Variable
Developed static and dynamic
quantizer models; provided de-
sign criteria linking ADC/DPWM
bits and loop gain for no-LCO
behavior.
Lukić et al., 2007
[4]
Buck (IC)
10 MHz
6
6 (multi-bit )
Proposed a multi-bit PWM
controller with fine effective duty
resolution beyond 10 MHz and
reduced low-frequency ripple via
noise shaping.
EJEEE 2025, Vol.3 67 of 75
steady-state limit cycles (LCOs) and derived conditions to avoid them, including the use
of controlled dithering [1]. Peng et al. extended the modelling to static and dynamic quan-
tizers, linking no-LCO behaviour to the interplay among ADC/DPWM resolution and
loop gain [3]. At higher frequencies, multi-bit PWM was proposed to improve effec-
tive duty resolution and shape low-frequency artefacts [4].
Overall, the literature establishes two themes: (i) adequate resolution or spectrum-
shaping techniques (dither, ) can mitigate quantization limits, and (ii) quantization in-
teracts with closed-loop dynamics in nonlinear ways that simple linear margins do not
capture. The gap this work addresses is an end-to-end, cross-topology view that ties ADC
resolution, fixed-point controller arithmetic, and DPWM realization together under MHz
timing constraints, and distils the outcome into simple, testable design rules. In particular,
we show that a single interpretable metric, (the ratio of the ADC LSB to the DPWM step
mapped through ), closely predicts the LCO boundary across buck, boost, and in-
verting buck–boost, and that dither/ recover roughly one to two effective DPWM bits
at 1 MHz.
2. Modeling and Methods
This section describes the non-ideal plant model, the digital control chain (ADC,
fixed–point controller, DPWM with dither and ), the timing model, the design-of-ex-
periments, and the acceptance metrics used to extract design rules.
2.1 Quantization at the ADC Stage
The ADC converts the sensed output to a digital word. With finite resolution, the
least-significant bit (LSB) introduces a voltage step
(1)
where is the ADC full-scale and is the bit depth. In regulation, bias is typ-
ically bounded within about 1 LSB [5]. In contemporary designs, meeting ac-
curacy at a low-voltage output can require roughly 10–12 bits [2]. If resolution is too
coarse, the output dithers around the set point and small errors must accumulate before
the controller reacts, slowing small-signal correction.
Low ADC resolution also interacts with the DPWM. If the smallest change the
DPWM can produce at the output exceeds , the loop may never find a zero-error
state and instead settle into an LCO. These discrete oscillations inject tones into the spec-
trum and make EMI harder to predict [3]. Pushing resolution higher at tens of MHz is
challenging: high-bit, high-rate sampling increases power, latency, and complexity, moti-
vating careful allocation of bits across the loop rather than simply maximizing ADC reso-
lution.
2.2 Controller Fixed-Point Quantization
Digital controllers are often implemented in fixed-point for efficiency. Coefficients
and internal states are stored with a limited number of integer and fractional bits, which
perturbs the intended gains and can slightly shift the loop transfer function. If rounding
and saturation are not handled carefully, phase/gain margins suffer. In many practical
designs, these effects are smaller than those from ADC and DPWM quantizers; nonethe-
less, the word length must be large enough that coefficient quantization does not intro-
duce material gain or phase error over the intended bandwidth. More fractional bits im-
prove dynamic range and reduce round-off noise, at the expense of silicon cost. In our
framework, controller quantization is included explicitly, and we show later that it is
rarely the dominant limiter when ADC and DPWM choices are reasonable.
To quantify the sensitivity of the control loop to arithmetic precision, we performed
a simulation sweep of the controller word length () from 8 to 24 bits for a 1 MHz buck
converter scenario. As shown in Figure 1, reducing below 14 bits leads to numerical
saturation and loss of stability, resulting in excessive output ripple. Above 14 bits, the
EJEEE 2025, Vol.3 68 of 75
quantization noise from the controller becomes negligible compared to the ADC and
DPWM quantization. Consequently, a word length of 24 bits (with 16 bits for the fractional
part) was selected for all subsequent analyses to ensure that arithmetic precision is not the
dominant source of error.
Figure 1. Impact of Controller Fixed-Point Resolution on Performance.
2.3 DPWM Resolution and Dithering
The DPWM converts the controller output into a duty ratio with a finite step of
each switching period. Mapped to the output, the smallest duty step produces
approximately
(2)
A widely used rule is therefore to size the DPWM so that [1]; if not,
one duty step can overshoot an ADC bin and induce LCOs. When a very fine base resolu-
tion is impractical, dithering averages between neighboring codes to realize sub-LSB steps
on average [2]. Controlled dithering can add roughly one effective bit without a larger
DPWM clock, but long patterns push energy to low frequencies (e.g., for a 4-cycle
pattern), which the output filter attenuates poorly, raising ripple and complicating EMI.
First-order modulation is another option: it shapes quantization energy to higher fre-
quencies while preserving average duty, improving effective resolution with a different
spectral signature. In all cases, the co-design goal is to obtain enough effective duty gran-
ularity without paying an excessive penalty in ripple or clock rate.
2.4 Effects on Performance, Stability, and EMI
Quantization affects operation in three visible ways. First, in steady state, insufficient
resolution at the ADC or DPWM forces the output to toggle between discrete levels, low-
ering accuracy and potentially producing LCOs [1]. Second, in frequency, these oscilla-
tions appear as discrete tones that can dominate the ripple spectrum and complicate EMI
compliance [3]. Third, in dynamics, small errors may not be corrected until they grow to
one LSB, yielding stepped responses and slower settling.
The nonlinearity of quantizers means conventional linear stability margins do not tell
the whole story. As shown in prior work, avoiding LCOs requires matching resolution
across the loop and managing loop gain [3]. A practical and interpretable condition is to
ensure the DPWM step, when mapped through the plant sensitivity , is not larger
than the ADC LSB; this aligns well with observed no-LCO behaviour in our simulations.
2.5 High-Frequency GaN Converter Trade-offs
At MHz switching, the same quantization issues become more acute. Faster loops
shrink the available time for sampling and computation, so latency consumes a larger
fraction of . If very fine DPWM steps are demanded at high , the corresponding time
EJEEE 2025, Vol.3 69 of 75
resolution pushes the DPWM clock into the multi-GHz range [1, 4]. That increases digital
power and area, and may itself introduce jitter. On the other hand, GaN transitions can be
shaped (e.g., resonant or soft-switching) to reduce EMI even as edges get faster [24]. De-
signers therefore face a coupled trade-off: resolution vs. clocking, latency vs. margin, and
filtering vs. spectral placement of quantization artifacts. Our results indicate that modest
increases in DPWM resolution (or use of dithering/) together with small delay fractions
can preserve stability and millivolt-level regulation at 1–10 MHz, while avoiding the need
for extreme clock rates.
2.6 Plant Models and Operating Points
We study three topologies: buck, boost, and inverting buck–boost. Unless stated oth-
erwise, the plant includes capacitor ESR (), inductor DCR (), MOSFET on-re-
sistance (), diode forward drop (), and dead-time . Operating points are cho-
sen so that the converter remains in CCM for the cases reported. Switching frequencies
are 1, 5, and 10 MHz.
2.7 Digital Control Chain
The loop is fully digital. The ADC samples the sensed output; a fixed-point PI con-
troller with anti-windup updates the duty command; and a DPWM block generates gate
pulses. Controller states and coefficients use a word length and fractional part .
Anti-windup limits the integrator when the duty saturates.
2.8 Quantization Models
The ADC is modeled as a mid-tread quantizer with least-significant bit (LSB)
(3)
where is the ADC full-scale and is the bit depth. The DPWM resolution is
per switching period. The corresponding voltage step is approximated
by
(4)
We define
(5)
and use as an interpretable no–LCO guideline. Two DPWM extensions are
considered: (i) dither, which averages adjacent codes over a short pattern (e.g., 4 cycles),
and (ii) first-order , which shapes quantization energy to higher frequencies while pre-
serving average duty.
2.9 Timing and Latency
Sampling and computation delays are modelled explicitly as fractions of : an ADC
aperture/sample delay and a digital compute/pipeline delay. Total delay is swept in the
0.03–0.06 range to reflect MHz control pipelines. Dead-time reduces the effective duty
by .
Physically, increasing the loop delay reduces the phase margin, making the converter
more susceptible to oscillations and instability, especially at high switching frequencies
where the period is very short.
EJEEE 2025, Vol.3 70 of 75
2.10 Design-of-Experiments
The selected switching frequencies (1, 5, and 10 MHz) span the transition from con-
ventional silicon-based designs to modern high-speed GaN applications, allowing us to
observe how quantization constraints tighten as the time budget shrinks. For each topol-
ogy and MHz we sweep and
on a compact grid, with and without dither/. The simulation step is to
and each run spans 2000–3000 periods. A short auto-tune pass picks PI gains that remove
DC bias and maintain margin under the chosen delays.
2.11 Metrics and Acceptance Criteria
We record: (i) steady-state bias
, (ii) output ripple (pk–pk), (iii) limit-cycle
occurrence (LCO) via a spectral test that flags dominant tones in –, (iv) an esti-
mate of from small duty perturbations, and (v) the ratio . A configuration is
accepted if it satisfies: no LCO, ripple or (as specified), , and
. Heat maps over and a consolidated design-rules table (minimal bit
pairs meeting the targets) are reported. In practice, designers can read the maps by select-
ing ADC/DPWM bit pairs that both satisfy the ripple target and keep ρ ≥ 1, since points
with ρ < 1 almost always fall into the LCO-dominated regions.
2.12 Validation Panels
Four checks are used to support validity: (1) analytic vs. simulated over duty
slices; (2) –versus–LCO boundary slices at fixed ; (3) sensitivity to , , , ADC
noise, and sampling jitter; and (4) a fixed-point ablation (varying controller fractional bits).
These show that the boundary aligns with LCO onset, that design rules are robust
to moderate parameter variation, and that controller fixed-point is not the dominant lim-
iter.
3. Results and Discussion
We report ripple and limit-cycle behaviour over the grid for three
converter topologies (buck, boost, inverting buck–boost) and multiple switching frequen-
cies. Unless stated, plots show ripple (pk–pk). When present, a black contour denotes
; regions to the right/up of this contour tend to be no-LCO and low-ripple.
3.1. Across-Topology Baselines at 1, 5, and 10 MHz
Figure 2 collects the baseline (non-dithered, non-) ripple maps for the three topol-
ogies at 1, 5, and 10 MHz. As increases, the feasible region shifts toward higher
DPWM bits due to tighter timing and larger effective duty sensitivity. At a fixed fre-
quency, boost and buck–boost require finer DPWM than buck for the same ripple target,
tracking the larger . These trends confirm that moving toward multi-MHz oper-
ation significantly increases design complexity and hardware demands, because accepta-
ble ripple limits can only be met with higher DPWM resolution and tighter timing control.
3.2. Effective-Resolution Gains from Dither and at 1 MHz
At 1 MHz, both dither and first-order expand the feasible region by roughly one
to two effective DPWM bits relative to the baseline; tends to push quantization energy
upward in frequency, which can aid EMI if the output filter prioritizes low-frequency at-
tenuation. Figure 3 compares these two techniques across the three topologies at 1 MHz.
These benefits, however, rely on an output filter with sufficient high-frequency attenua-
tion; inadequate filter design can significantly reduce the effective advantage of dither or
Sigma-Delta modulation.
3.3. Condensed Design Rules
Table 2. lists the minimal pairs that satisfy the acceptance criteria
(no LCO, , ) for ripple targets of and . Baseline entries
EJEEE 2025, Vol.3 71 of 75
are reported at 1/5/10 MHz; dither and entries are reported at 1 MHz. A “–” indicates
the criteria were not simultaneously achieved on the scanned grid.
3.4. Interpretation
Three patterns recur across all datasets: (i) the boundary aligns with the onset
of LCO and delineates low-ripple regions; (ii) boost and buck–boost require higher
DPWM resolution than buck at a given ripple target; and (iii) increasing or effective
delay shifts the feasible region toward higher . At 1 MHz, modest dither or
first-order typically recovers 1–2 effective bits without extreme DPWM clock rates.
3.5. Limitations
This study focuses on establishing the theoretical bounds of quantization in ideal
switching conditions. While the simulation model incorporates key non-ideal ties such as
delays, , and dead-time, it does not account for second-order hardware effects like
switching jitter noise or variable EMI filter impedance. However, the derived design rules
are intentionally conservative (requiring ). These rules provide a 'safe operating ar-
ea' for designers; if a configuration is stable in this rigorous simulation, it is highly likely
to be stable in hardware, though the exact ripple magnitude may vary. Future work will
focus on hardware-in-the-loop validation to calibrate these boundaries against experi-
mental GaN prototypes.
Figure 2. Baseline output voltage ripple maps over at 1, 5, and 10 MHz. Rows represent buck
(top), boost (middle), and inverting buck–boost (bottom) topologies. Dark blue regions correspond to stable,
low-ripple operation (no limit cycles), while yellow/green regions indicate high ripple or limit-cycle oscillations
due to coarse quantization.
EJEEE 2025, Vol.3 72 of 75
Table 2. Minimal pairs meeting no-LCO, , and at two ripple targets.
Entries show ADC/DPWM bits; “–” indicates not achieved on the scanned grid.
Topology
Mode
(MHz)
mV
mV
buck
baseline
1
8/9
–
buck
baseline
5
10/11
–
buck
baseline
10
–
–
buck
dither
1
8/8
11/8
buck
1
8/8
11/8
boost
baseline
1
10/12
–
boost
baseline
5
–
–
boost
baseline
10
–
–
boost
dither
1
9/11
10/11
boost
1
9/11
10/11
Buck-boost
baseline
1
–
–
Buck-boost
baseline
5
–
–
Buck-boost
baseline
10
–
–
Buck-boost
dither
1
–
–
Buck-boost
1
–
–
Figure 3. Comparison of dither (left column) and first-order (right column) modulation at 1 MHz for
buck (top), boost (middle), and inverting buck–boost (bottom). Both techniques significantly expand the
low-ripple (dark blue) region compared to the baseline, allowing for reduced bit depths while maintaining
stability.
EJEEE 2025, Vol.3 73 of 75
4. Conclusion
This work studied end-to-end quantization co-design for digitally controlled MHz-
range GaN converters, covering the ADC, fixed-point controller, and DPWM. Using a uni-
form simulation pipeline, we swept across buck, boost, and inverting
buck–boost topologies at 1, 5, and 10 MHz. Three consistent findings emerge: first, the
boundary tracks the onset of limit-cycle oscillations (LCOs); second, boost and
buck–boost topologies require higher DPWM resolution than buck due to larger ;
and third, increasing shifts the feasible region toward higher bit depths. At 1 MHz,
modest dithering or first-order recovers about 1–2 effective bits, relaxing clocking de-
mands. For practitioners, we recommend identifying the smallest bit-pair from the gener-
ated ripple maps that satisfies , then enabling dither/ if the region is tight. While
this study is based on conservative, idealized simulations, the derived rules provide a safe
starting point for hardware prototyping, with future work planned to validate these find-
ings against parasitic and jitter measurements in GaN experimental setups.
EJEEE 2025, Vol.3 74 of 75
References
1. Peterchev, A.V. and S.R. Sanders, Quantization resolution and limit cycling in digitally controlled PWM converters. 2001 IEEE
32nd Annual Power Electronics Specialists Conference (IEEE Cat. No.01CH37230), 2001. 2: p. 465-471 vol.2.
2. Patella, B.J.F.C., et al., High-frequency digital PWM controller IC for DC-DC converters. IEEE Transactions on Power Electronics,
2003. 18: p. 438-446.
3. Peng, H., et al., Modeling of Quantization Effects in Digitally Controlled DC–DC Converters. IEEE Transactions on Power
Electronics, 2004. 22: p. 208-215.
4. Lukić, Z., N. Rahman, and A. Prodić, Multibit $\Sigma$–$\Delta$ PWM Digital Controller IC for DC–DC Converters Operating
at Switching Frequencies Beyond 10 MHz. IEEE Transactions on Power Electronics, 2007. 22: p. 1693-1707.
5. Prodić, A., D. Maksimović, and R.W. Erickson, Design and implementation of a digital PWM controller for a high-frequency
switching DC-DC power converter. IECON'01. 27th Annual Conference of the IEEE Industrial Electronics Society (Cat.
No.37243), 2001. 2: p. 893-898 vol.2.
6. Erickson, R.W. and D. Maksimović. Fundamentals of Power Electronics. 2001.
7. Peterchev, A., Digital pulse-width modulation control in power electronic circuits: Theory and applications. Ph.D. thesis, UC
Berkeley,, 2005.
8. Sanders, A.V.P.a.S.R., Quantization Resolution and Limit Cycling—Extended Analysis. UC Berkeley Tech. Rep. EECS, 2006: p.
20006-22.
9. Buso, S. and P. Mattavelli. Digital Control in Power Electronics. in Synthesis Lectures on Power Electronics. 2006.
10. Hagen, M.D. and V. Yousefzadeh. Applying Digital Technology to PWM Control-Loop Designs. 2008.
11. Corradini, L., et al. Digital control of high-frequency switched-mode power converters. 2015.
12. González-Castaño, C., et al., ADC Quantization Effects in Two-Loop Digital Current Controlled DC-DC Power Converters: Analysis
and Design Guidelines. Applied Sciences, 2020.
13. Sajitha, G., Methods for eliminating the limit cycle oscillation due to low resolution ADC/DPWM in digitally controlled DC-DC
converters. Ph.D. thesis, IIST, 2018.
14. Chander, S., P. Agarwal, and I. Gupta, ASIC and FPGA based DPWM architectures for single-phase and single-output DC-DC
converter: a review. Central European Journal of Engineering, 2013. 3: p. 620-643.
15. Scharrer, M., M. Halton, and T. Scanlan. FPGA-Based Digital Pulse Width Modulator With Optimized Linearity. in 2009 Twenty-
Fourth Annual IEEE Applied Power Electronics Conference and Exposition. 2009. DOI: 10.1109/APEC.2009.4802819.
16. Wu, F.-Y., Y.-M. Chen, and C.-W. Chen, Impact of PWM jitter to switching-mode power converter efficiency. 2013 15th European
Conference on Power Electronics and Applications (EPE), 2013: p. 1-8.
17. Balcells, J., et al., EMI reduction in switched power converters using frequency Modulation techniques. IEEE Transactions on
Electromagnetic Compatibility, 2005. 47: p. 569-576.
18. Ustun Ercan, S., A. Pena-Quintal, and D. Thomas, The Effect of Spread Spectrum Modulation on Power Line Communications.
Energies, 2023. 16(13): p. 5197.
19. Stok, E., et al., EMI Reduction in an Interleaved Buck Converter Through Spread Spectrum Frequency Modulation. 2023 25th
European Conference on Power Electronics and Applications (EPE'23 ECCE Europe), 2023: p. 1-11.
20. Rivas, J.M., et al., A Very High Frequency DC–DC Converter Based on a Class ${\bm \Phi}_{\bm 2}$ Resonant Inverter. IEEE
Transactions on Power Electronics, 2011. 26: p. 2980-2992.
21. Hariya, A., et al., 5MHz PWM-controlled current-mode resonant DC-DC converter using GaN-FETs. 2014 International Power
Electronics Conference (IPEC-Hiroshima 2014 - ECCE ASIA), 2014: p. 3630-3637.
22. Beohar, N., et al., A Digitally Controlled DC-DC Buck Converter with Automatic Digital PFM to PWM Transition Scheme. 2021
IEEE Applied Power Electronics Conference and Exposition (APEC), 2021: p. 517-522.
EJEEE 2025, Vol.3 75 of 75
23. Savio, S., et al., Digital Control of a Multilevel Interleaved DC-DC GaN Converter for Fuel Cell Traction Applications. 2024 IEEE
Energy Conversion Congress and Exposition (ECCE), 2024: p. 4484-4490.
24. Thummala, P., et al., A 10-MHz GaNFET-Based-Isolated High Step-Down DC–DC Converter: Design and Magnetics Investigation.
IEEE Transactions on Industry Applications, 2019. 55: p. 3889-3900.
